SH7615 Datasheet, PDF (481/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

10.2.12 Receiver Control Register (RCR)
RCR specifies the control method for the RE bit in ECMR when a frame is received.
Note: When setting this register, do so in the receiving-halt state.
Bit: 31
30
29
...
11
10
9
8
—
—
—
...
—
—
—
—
Initial value: 0
0
0
...
0
0
0
0
R/W: R
R
R
...
R
R
R
R
Bit: 7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
RNC
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R/W
Bits 31 to 1—Reserved: These bits are always read as 0. The write value should always be 0.
Bit 0—Receive Enable Control (RNC)
Bit 0: RNC
Description
0
When reception of one frame is completed, the E-DMAC writes the receive
status into the descriptor and clears the RR bit in EDRRR
(Initial value)
1
When reception of one frame is completed, the E-DMAC writes the receive
status into the descriptor, reads the next descriptor, and prepares to receive
the next frame^*
Note: * This setting is normally used for continuous frame reception.
Rev. 2.00, 03/05, page 443 of 884