SH7615 Datasheet, PDF (519/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

11.3.2 DMA Transfer Requests
DMA transfer requests are usually generated in either the data transfer source or destination, but
they can also be generated by devices that are neither the source nor the destination. Transfers can
be requested in three modes: auto-request, external request, and on-chip peripheral module
request. The request mode is selected with the AR bit in DMA channel control registers 0 and 1
(CHCR0, CHCR1) and the RS0, RS1, RS2, RS3 and RS4 bits in DMA request/response selection
control registers 0 and 1 (DRCR0, DRCR1).
Table 11.3 Selecting the DMA Transfer Request Using the AR and RS Bits
CHCR
DRCR
AR
RS4 RS3 RS2 RS1 RS0 Request Mode
0
0
0
0
0
0
Module request mode
1
0
1
10
1
0
0
1
10
1
0
1
10
1
1
0
0
0
10
1
0
1
10
1
0
0
1
10
1
*
*
*
*
*
Auto-request mode
Note: * Don’t care
Resource Selection
DREQ (external request)
SCIF channel 1 RXI
SCIF channel 1 TXI
SCIF channel 2 RXI
SCIF channel 2 TXI
TPU TGI0A
TPU TGI0B
TPU TGI0C
TPU TGI0D
SIO channel 0 RDFI
SIO channel 0 TDEI
SIO channel 1 RDFI
SIO channel 1 TDEI
SIO channel 2 RDFI
SIO channel 2 TDEI
Auto-Request Mode: When there is no transfer request signal from an external source (as in a
memory-to-memory transfer, the auto-request mode allows the DMAC to automatically generate a
transfer request signal internally. When the DE bits in CHCR0 and CHCR1 and the DME bit in
the DMA operation register (DMAOR) are set to 1, the transfer begins (so long as the TE bits in
CHCR0 and CHCR1 and the NMIF and AE bits in DMAOR are all 0).
Rev. 2.00, 03/05, page 481 of 884