SH7615 Datasheet, PDF (543/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

When external memory is set as bank active synchronous DRAM, during a write the acknowledge
signal is output across the wait and column address when the row address is the same as the
previous address output (figure 11.26). When the row address is different from the previous
address, the acknowledge signal is output across the precharge, row address, wait and column
address (figure 11.27).
Clock
DACKn
(Active high)
Address
bus
Column
address
DMAC write
(basic timing)
Figure 11.26 DACKn Output in Synchronous DRAM Write
(Bank Active, Same Row Address, AM = 1)
Clock
DACKn
(Active high)
Address
bus
Row Column
Precharge address address
DMAC write
(basic timing)
Figure 11.27 DACKn Output in Synchronous DRAM Write
(Bank Active, Different Row Address, AM = 1)
Rev. 2.00, 03/05, page 505 of 884