SH7615 Datasheet, PDF (468/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

Bit 16—Receive FIFO Overflow (RFOF): Indicates that the receive FIFO has overflowed during
frame reception.
Bit 16: RFOF Description
0
Overflow has not occurred
(Initial value)
1
Overflow has occurred (interrupt source)
Notes: 1. If there are a number of receive frames in the receive FIFO, they will not be sent to
memory correctly. The status of the frame that caused the overflow is written back to
the receive descriptor.
2. Whether E-DMAC operation continues or halts after overflow is controlled by the E-
DMAC operation control register (EDOCR).
Bits 15 to 13—Reserved: These bits are always read as 0. The write value should always be 0.
Bit 12—Illegal Transmit Frame (ITF): Indicates that the transmit frame length specification is less
than four bytes.
Bit 12: ITF
0
1
Description
Normal transmit frame length
Illegal transmit frame length (interrupt source)
(Initial value)
Bit 11—Carrier Not Detect (CND): Indicates the carrier detection status.
Bit 11: CND
0
1
Description
A carrier is detected when transmission starts
Carrier not detected (interrupt source)
(Initial value)
Bit 10—Detect Loss of Carrier (DLC): Indicates that loss of the carrier has been detected during
frame transmission.
Bit 10: DLC
0
1
Description
Loss of carrier not detected
Loss of carrier detected (interrupt source)
(Initial value)
Bit 9—Delayed Collision Detect (CD): Indicates that a delayed collision has been detected during
frame transmission.
Bit 9: CD
0
1
Description
Delayed Collision not detected
Delayed Collision detected (interrupt source)
(Initial value)
Rev. 2.00, 03/05, page 430 of 884