SH7615 Datasheet, PDF (674/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

14.5 Usage Notes
The following points should be noted when using the SCIF.
SCFTDR Writing and the TDFE Flag: The TDFE flag in the serial status 1 register (SC1SSR)
is set when the number of transmit data bytes written in the transmit FIFO data register (SCFTDR)
has fallen to or below the transmit trigger number set by bits TTRG1 and TTRG0 in the FIFO
control register (SCFCR). After TDFE is set, transmit data up to the number of empty bytes in
SCFTDR can be written, allowing efficient continuous transmission.
However, if the number of data bytes written in SCFTDR is equal to or less than the transmit
trigger number, the TDFE flag will be set to 1 again after being read as 1 and cleared to 0. TDFE
clearing should therefore be carried out when SCFTDR contains more than the transmit trigger
number of transmit data bytes.
The number of transmit data bytes in SCFTDR can be found from the upper 8 bits of the FIFO
data count register (SCFDR).
Simultaneous Multiple Receive Errors: If a number of receive errors occur at the same time, the
state of the status flags in SC1SSR and SC2SSR is as shown in table 14.14. If there is an overrun
error, data is not transferred from the receive shift register (SCRSR) to the receive FIFO data
register (SCFRDR), and the receive data is lost.
Table 14.14 SC1SSR/SC2SSR Status Flags and Transfer of Receive Data
SC1SSR/SC2SSR Status Flags
Receive Errors
RDF ORER FER PER
Overrun error
1
1
0
0
Framing error
0
0
1
0
Parity error
0
0
0
1
Overrun error + framing error
1
1
1
0
Overrun error + parity error
1
1
0
1
Framing error + parity error
0
0
1
1
Overrun error + framing error + 1
1
1
1
parity error
Note: O: Receive data is transferred from SCRSR to SCFRDR.
×: Receive data is not transferred from SCRSR to SCFRDR.
Receive Data Transfer
SCRSR → SCFRDR
×
O
O
×
×
O
×
Rev. 2.00, 03/05, page 636 of 884