SH7615 Datasheet, PDF (202/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

As table 5.5 shows, between two and four on-chip peripheral modules are assigned to each
interrupt priority level setting register. Set the priority levels by setting the corresponding 4-bit
groups with values in the range of H'0 (0000) to H'F (1111). H'0 is interrupt priority level 0 (the
lowest); H'F is level 15 (the highest). When two on-chip peripheral modules are assigned to the
same bits (DMAC0 and DMAC1, or WDT and BSC refresh control unit), those two modules have
the same priority. A reset initializes IPRA to IPRE to H'0000. They are not initialized in standby
mode.
5.3.6 Vector Number Setting Register WDT (VCRWDT)
Vector number setting register WDT (VCRWDT) is a 16-bit read/write register that sets the WDT
interval interrupt and BSC compare match interrupt vector numbers (0 to 127). VCRWDT is
initialized to H'0000 by a reset. It is not initialized in standby mode.
Bit: 15
14
13
12
11
10
9
8
— WITV6 WITV5 WITV4 WITV3 WITV2 WITV1 WITV0
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R/W R/W R/W R/W R/W R/W R/W
Bit: 7
6
5
4
3
2
1
0
— BCMV6 BCMV5 BCMV4 BCMV3 BCMV2 BCMV1 BCMV0
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R/W R/W R/W R/W R/W R/W R/W
Bits 15 and 7—Reserved: These bits are always read as 0. The write value should always be 0.
Bits 14 to 8—Watchdog Timer (WDT) Interval Interrupt Vector Number 6 to 0 (WITV6 to
WITV0): These bits set the vector number for the interval interrupt (ITI) of the watchdog timer
(WDT). There are seven bits, so the value can be set between 0 and 127.
Bits 6 to 0—Bus State Controller (BSC) Compare Match Interrupt Vector Number 6 to 0
(BCMV6 to BCMV0): These bits set the vector number for the compare match interrupt (CMI) of
the bus state controller (BSC). There are seven bits, so the value can be set between 0 and 127.
Rev. 2.00, 03/05, page 164 of 884