SH7615 Datasheet, PDF (421/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

Bits 11 and 10—Reserved: These bits are always read as 0. The write value should always be 0.
Bit 9—Magic Packet Detection Enable (MPDE): Enables or disables Magic Packet detection by
hardware to allow activation from the Ethernet. When the Magic Packet is detected, it is reflected
to the EtherC status register and the WOL pin notifies peripheral LSIs that the Magic Packet has
been received.
Bit 9: MPDE
0
1
Description
Magic Packet detection is not enabled
Magic Packet detection is enabled
(Initial value)
Bits 8 and 7—Reserved: These bits are always read as 0. The write value should always be 0.
Bit 6—Receiver Enable (RE): Enables or disables the receiver.
Bit 6: RE
Description
0
Receiver is disabled
(Initial value)
1
Receiver is enabled
Note: If a switch is made from the receiver-enabled state (RE = 1) to the receiver-disabled state
(RE = 0) while a frame is being received, the receiver will not be disabled until reception of
the frame is completed.
Bit 5—Transmitter Enable (TE): Enables or disables the transmitter.
Bit 5: TE
Description
0
Transmitter is disabled
(Initial value)
1
Transmitter is enabled
Note: If a switch is made from the transmitter-enabled state (TE = 1) to the transmitter-disabled
state (TE = 0) while a frame is being transmitted, the transmitter will not be disabled until
transmission of the frame is completed.
Bit 4—Reserved: This bit is always read as 0. The write value should always be 0.
Bit 3—Internal Loop Back Mode (ILB): Specifies loopback mode in the EtherC.
Bit 3: ILB
Description
0
Normal data transmission/reception is performed
(Initial value)
1
Data loopback is performed inside the EtherC
Note: A loopback mode specification can only be made with full-duplex transfer (DM = 1 in this
register).
Rev. 2.00, 03/05, page 383 of 884