SH7615 Datasheet, PDF (756/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

TGF Flag Setting Timing in Case of Input Capture: Figure 16.39 shows the timing for setting
of the TGF flag in TSR by input capture occurrence, and TGI interrupt request signal timing.
Pφ
Input capture
signal
TCNT
N
TGR
N
TGF flag
TGI interrupt
Figure 16.39 TGI Interrupt Timing (Input Capture)
TCFV Flag/TCFU Flag Setting Timing: Figure 16.40 shows the timing for setting of the TCFV
flag in TSR by overflow occurrence, and TCIV interrupt request signal timing.
Figure 16.41 shows the timing for setting of the TCFU flag in TSR by underflow occurrence, and
TCIU interrupt request signal timing.
Pφ
TCNT input
clock
TCNT
(overflow)
Overflow
signal
TCFV flag
H'FFFF
H'0000
TCIV interrupt
Figure 16.40 TCIV Interrupt Setting Timing
Rev. 2.00, 03/05, page 718 of 884