SH7615 Datasheet, PDF (89/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

Table 2.6 Sign Extension of Word Data
SH7615 CPU
Description
Example of Conventional CPU
MOV.W @(disp,PC),R1
ADD
R1,R0
........
.DATA.W H'1234
Data is sign-extended to 32 ADD.W
bits, and R1 becomes
H'00001234. It is next operated
upon by an ADD instruction
#H'1234,R0
Note: @(disp, PC) accesses the immediate data.
Load-Store Architecture: Basic operations are executed between registers. For operations that
involve memory access, data is loaded to the registers and executed (load-store architecture).
However, Instructions such as AND manipulating bits, are executed directly in memory.
Delayed Branches: Such instructions as unconditional branches are delayed branch instructions.
In the case of delayed branch instructions, the branch occurs after execution of the instruction
immediately following the delayed branch instruction (slot instruction). This reduces pipeline
disruption during branching.
The branching operation of the delayed branch occurs after execution of the slot instruction.
However, with the exception of such branch operations as register updating, execution of
instructions is performed with the order of delayed branch instruction, then delayed slot
instruction.
For example, even if the contents of a register storing a branch destination address are modified by
a delayed slot, the branch destination address will still be the contents of the register before the
modification.
Table 2.7 Delayed Branch Instructions
SH7615 CPU
BRA TRGET
ADD R1,R0
Description
Executes an ADD before
branching to TRGET
Example of Conventional CPU
ADD.W R1,R0
BRA TRGET
Multiplication/Multiply-Accumulate Operation: 16 × 16 → 32 multiplications execute in one
to three cycles, and 16 × 16 + 64 → 64 multiply-accumulate operations execute in two to three
cycles. 32 × 32 → 64 multiplications and 32 × 32 + 64 → 64 multiply-accumulate operations
execute in two to four cycles.
Rev. 2.00, 03/05, page 51 of 884