SH7615 Datasheet, PDF (828/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

The clock pause state can be canceled by means of NMI input, in the same way as the normal
standby state. The clock pause request should be canceled within four CKIO clock cycles after
NMI input. Figure 20.4 shows the timing chart for clock pause state cancellation by means of NMI
input (in the case of rising edge detection).
CKIO input
Frequency
modification
Max. 4 cycles
CKPREQ/
CKM input
NMI input
Clock pause request
cancellation
CKPACK
output
NMI interrupt
Clock pause
acceptance
processing
Clock pause state
Normal state
Figure 20.4 Clock Pause Function Timing Chart (Cancellation by NMI Input)
20.4.5 Notes on Standby Mode
1. When the chip enters standby mode during use of the cache, disable the cache before making
the mode transition. Initialize the cache beforehand when the cache is used after returning to
standby mode. The contents of the on-chip RAM are not retained in standby mode when cache
is used as on-chip RAM.
2. If an on-chip peripheral register is written in the 10 clock cycles before the chip transits to
standby mode, read the register before executing the SLEEP instruction.
3. When using clock mode 0, 1, or 2, the CKIO pin is the clock output pin. Note the following
when standby mode is used in these clock modes. When standby mode is canceled by NMI, an
unstable clock is output from the CKIO pin during the oscillation settling time after NMI
input. This also applies to clock output in the case of cancellation by a power-on reset or
manual reset. Power-on reset and manual reset input should be continued for a period at least
equal to for the oscillation settling time.
4. Before entering the standby mode, stop operation of the internal DMAC (E-DMAC or
DMAC).
Rev. 2.00, 03/05, page 790 of 884