SH7615 Datasheet, PDF (118/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

Table 2.21 Arithmetic Instructions
Instruction
Instruction Code
ADD
Rm,Rn 0011nnnnmmmm1100
ADD
#imm,Rn 0111nnnniiiiiiii
ADDC Rm,Rn 0011nnnnmmmm1110
ADDV Rm,Rn 0011nnnnmmmm1111
CMP/EQ #imm,R0 10001000iiiiiiii
Operation
Rn + Rm → Rn
Rn + imm → Rn
Rn + Rm + T → Rn,
Carry → T
Rn + Rm → Rn,
Overflow → T
If R0 = imm, 1 → T
Cycles
1
1
1
1
1
CMP/EQ Rm,Rn 0011nnnnmmmm0000 If Rn = Rm, 1 → T
1
CMP/HS Rm,Rn
CMP/GE Rm,Rn
CMP/HI Rm,Rn
CMP/GT Rm,Rn
CMP/PL Rn
0011nnnnmmmm0010
0011nnnnmmmm0011
0011nnnnmmmm0110
0011nnnnmmmm0111
0100nnnn00010101
If Rn ≥ Rm with unsigned 1
data, 1 → T
If Rn ≥ Rm with signed 1
data, 1 → T
If Rn > Rm with unsigned 1
data, 1 → T
If Rn > Rm with signed 1
data, 1 → T
If Rn > 0, 1 → T
1
CMP/PZ Rn
0100nnnn00010001 If Rn ≥ 0, 1 → T
1
CMP/STR Rm,Rn
DIV1 Rm,Rn
DIV0S Rm,Rn
DIV0U
DMULS.L Rm,Rn
DMULU.L Rm,Rn
0010nnnnmmmm1100
0011nnnnmmmm0100
0010nnnnmmmm0111
0000000000011001
0011nnnnmmmm1101
0011nnnnmmmm0101
If Rn and Rm contain 1
an identical byte,
1→T
Single-step division
1
(Rn/Rm)
MSB of Rn → Q, MSB 1
of Rm → M, M ^ Q → T
0 → M/Q/T
1
Signed operation of Rn × 2 to 4^*
Rm → MACH, MACL
32 × 32 → 64 bits
Unsigned operation of
Rn × Rm → MACH,
MACL 32 × 32 →
64 bits
2 to 4^*
T Bit
—
—
Carry
Overflow
Comparison
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Rev. 2.00, 03/05, page 80 of 884