SH7615 Datasheet, PDF (405/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

Iφ
CPU
pipeline EX
MA
stage
EX
MA
Cache
address
bus
Cache
data bus
Address A
Cache tag comparison
Address B
Address A
Cache tag comparison
Internal
address
bus
Internal
data bus
Data array write
Address A
+4
Address A
+8
Address A
+12
Address A
Address A
+4
Address A
+8
Address A
+12
Address A
EX: Instruction execution
MA: Memory access
Figure 8.7 Write Access in Case of a Cache Miss (Write-Back)
When the update bit of an entry to be replaced in write-back mode is 1, write-back to external
memory is necessary. To improve performance, the entry to be replaced is first transferred to the
write-back buffer, and fetching of the new entry into the cache is given priority over the write-
back. When the new entry has been fetched into the cache, the write-back buffer contents are
written back to external memory. The cache can be accessed during this write-back.
The write-back buffer can hold one cache line (16 bytes) of data and its address. The configuration
of the write-back buffer is shown in figure 8.8.
A (31–4) Longword 0 Longword 1 Longword 2 Longword 3
A (31–4):
Address for write-back to external memory
Longwords 0–3: One cache line of data for write-back to external memory
Figure 8.8 Write-Back Buffer Configuration
Rev. 2.00, 03/05, page 367 of 884