SH7615 Datasheet, PDF (839/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

21.3.2 Control Signal Timing
Table 21.6 Control Signal Timing
Conditions: V_CC = PLLV_CC = 3.3 V ±0.3 V, PV_CC = 5.0 V ± 0.5 V/3.3 V ±0.3 V, PV_CC ≥ V_CC,
V_SS = PV_SS = PLLV_SS = 0 V, Ta = –20 to +75°C
Item
Symbol Min
Max
Unit Figure
RES rise and fall time
RES pulse width
t_RESr,
—
t_RESf
t_RESW
20
200
ns
21.9
—
t_Pcyc
NMI reset setup time
t_NMIRS
t_Pcyc + 10
—
ns
NMI reset hold time
t_NMIRH
t_Pcyc + 10
—
ns
NMI rise and fall time
RES setup time^*
NMI setup time^*
IRL3 to IRL0 setup time^*
t_NMIr,
t_NMIf
t_RESS
t_NMIS
t_IRLS
—
200
3t_Ecyc + 40 —
40
—
30
—
ns
ns
21.10
ns
ns
NMI hold time
IRL3 to IRL0 hold time^*
BRLS setup time
BRLS hold time
BGR delay time
t_NMIH
20
t_IRLH
20
t_BLSS
10
t_BLSH
5
t_BGRD
—
—
ns
—
ns
—
ns
21.11
—
ns
15
ns
Bus tri-state delay time
t_BOFF
0
35
ns
Bus buffer on time
t_BON
0
35
ns
Note: * The RES, NMI, and IRL3 to IRL0 signals are asynchronous inputs. If the setup times
shown here are observed, a transition is judged to have occurred at the fall of the clock;
if the setup times cannot be observed, recognition may be delayed until the next fall of
the clock.
tRESf
tRESr
RES
tNMIr
tNMIf
NMI
VIH
VIL
tNMIRS
VIH
VIL
tRESW
VIH
VIL
tNMIRH
VIH
VIL
Figure 21.9 Reset Input Timing
Rev. 2.00, 03/05, page 801 of 884