SH7615 Datasheet, PDF (15/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

Item
10.2.6 EtherC/E-DMAC
Status Register (EESR)
Page
426,
427
Revisions (See Manual for Details)
Bits 26 to 25
Description amended
Bit: 31
30
29
28
27
26
25
24
—
—
—
—
—
TABT RABT RFCOF
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R/W R/W R/W
Bits 31 to 27—Reserved: These bits are always read as 0. The write value should always read as 0.
Bit 26—Transmit abort detection (TABT): Indicates whether or not a transmit abort was detected.
Bit 26: TABT
0
1
Description
Transmit abort not detected
Transmit abort detected
(Initial value)
This bit will be set when any one or more of the following bits are set.
EESR bit 12: Illegal Transmit Frame (ITF)
EESR bit 11: Carrier Not Detected (CND)
EESR bit 10: Detect Loss of Carrier (DLC)
EESR bit 9: Delayed Collision Detect (CD)
Bit 25— Receive abort detected (RABT): Indicates whether or not a receive abort was detected.
Bit 25: RABT
0
1
Description
Receive abort not detected
Receive abort detected
(Initial value)
430
10.2.8 Transmit/Receive 437
Status Copy Enable
Register (TRSCER)
10.2.10 Transmit FIFO 440,
Threshold Register
441
(TFTR)
This bit will be set when any one or more of the following bits are set.
EESR bit 4: Receive Residual-Bit Frame (RRF)
EESR bit 3: Receive Too-Long Frame (RTLF)
EESR bit 2: Receive Too-Short Frame (RTSF)
EESR bit 1: PHY-LSI Receive Error (PRE)
EESR bit 0: CRC Error on Received Frame (CERF)
Bit 9—Delayed Collision Detect (CD)
Description amended
Bit 9—Delayed Collision Detect (CD): Indicates that a delayed collision has been detected during
frame transmission.
Bit 9: CD
0
1
Description
Delayed Collision not detected
Delayed Collision detected (interrupt source)
(Initial value)
• General description of register modified
• Bits 12 to 8, and 4 to 0 amended to reserved bits.
• Bit 7 Multicast Address Frame Receive (RMAF) Bit Copy
Enable (RMAFCE) added.
Restriction added
Rev. 2.00, 03/05, page xv of xxxviii