SH7615 Datasheet, PDF (111/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

Category
Mnemonic
31–27 26
Conditional ^{(if cc) PSHL Sx, Sy, Dz 1 0}
three ^{(if cc) PSHA Sx, Sy, Dz}
operand (if cc) PSUB Sx, Sy, Dz
instructions (if cc) PADD Sx, Sy, Dz
Reserved
(if cc) PAND Sx, Sy, Dz
(if cc) PXOR Sx, Sy, Dz
(if cc) POR Sx, Sy, Dz
(if cc) PDEC Sx, Dz
(if cc) PINC Sx, Dz
(if cc) PDEC Sy, Dz
(if cc) PINC Sy, Dz
(if cc) PCLR Dz
(if cc) PDMSB Sx, Dz
Reserved
(if cc) PDMSB Sy, Dz
(if cc) PNEG Sx, Dz
(if cc) PCOPY Sx, Dz
(if cc) PNEG Sy, Dz
(if cc) PCOPY Sy, Dz
Reserved
(if cc) PSTS MACH, Dz
(if cc) PSTS MACL, Dz
(if cc) PLDS Dz, MACH
(if cc) PLDS Dz, MACL
Reserved^*2
Reserved
1
25–16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
A field
0 0 0 0 if cc
01
10
11
01:
0 0 0 1 ^Uncon-
01
dition
10
11
0 0 1 0 ^10:DCT
01
10
11
0 0 1 1 ^11:DCF
01
10
11
11 0010
01
10
11
00
0 0 1 1 if cc
01
10
11
00
0*
Notes: 1. System reserved code
2. (if cc): DCT (DC bit true), DCF (DC bit false), or none (unconditional instruction)
2.5 Instruction Set
The instructions are divided into three groups: CPU instructions executed by the CPU core, DSP
data transfer instructions executed by the DSP unit, and DSP operation instructions. There are a
number of CPU instructions for supporting the DSP functions. The instruction set is explained
below in terms of each of the three groups.
Rev. 2.00, 03/05, page 73 of 884