SH7615 Datasheet, PDF (712/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

TIOR1
Bit 7: Bit 6: Bit 5: Bit 4:
Channel IOB3 IOB2 IOB1 IOB0 Description
1
0
0
0
0
TGR1B is Output disabled
(Initial value)
1
output _{Initial output is 0 0 output at compare match}
1
0
compare _output
register
1 output at compare match
1
Toggle output at compare
match
1
0
0
Output disabled
1
1
0
Initial output is 1 0 output at compare match
output
1 output at compare match
1
Toggle output at compare
match
1
0
0
0
TGR1B is Capture input Input capture at rising edge
1
input
source is TIOCB1 _{Input capture at falling edge}
capture pin
1
*
register
Input capture at both edges
1
*
*
Setting prohibited
*: Don’t care
TIOR2
Bit 7: Bit 6: Bit 5: Bit 4:
Channel IOB3 IOB2 IOB1 IOB0 Description
2
0
0
0
0
TGR2B is Output disabled
(Initial value)
1
output _{Initial output is 0 0 output at compare match}
1
0
compare _output
register
1 output at compare match
1
Toggle output at compare
match
1
0
0
Output disabled
1
1
0
Initial output is 1 0 output at compare match
output
1 output at compare match
1
Toggle output at compare
match
1
*
0
0
TGR2B is Capture input Input capture at rising edge
1
input
source is TIOCB2 _{Input capture at falling edge}
capture pin
1
*
register
Input capture at both edges
*: Don’t care
Rev. 2.00, 03/05, page 674 of 884