SH7615 Datasheet, PDF (316/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

The 8-bit counter RTCNT counts up with input clocks. The clock select bit of RTCSR selects an
input clock. RTCNT values can always be read/written by the CPU. When RTCNT matches
RTCOR, RTCNT is cleared. Returns to 0 after it counts up to 255.
Bits 15 to 8—Reserved: These bits are always read as 0. The write value should always be 0.
7.2.10 Refresh Time Constant Register (RTCOR)
Bit: 15
14
13
12
11
10
9
8
—
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
Bit: 7
6
5
4
3
2
1
0
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
RTCOR is an 8-bit read/write register. The values of RTCOR and RTCNT are constantly
compared. When the values correspond, the compare match flag (CMF) in RTCSR is set and
RTCNT is cleared to 0. When the refresh bit (RFSH) in the individual memory control register
(MCR) is set to 1, a refresh request signal occurs. The refresh request signal is held until refresh
operation is actually performed. If the refresh request is not processed before the next match, the
previous request becomes ineffective.
When the CMIE bit in RTCSR is set to 1, an interrupt request is sent to the controller by this
match signal. The interrupt request is output continuously until the CMF bit in RTCSR is cleared.
When the CMF bit clears, it only affects the interrupt; the refresh request is not cleared by this
operation. When a refresh is performed and refresh requests are counted using interrupts, a refresh
can be set simultaneously with the interval timer interrupt.
Bits 15 to 8—Reserved: These bits are always read as 0. The write value should always be 0.
Rev. 2.00, 03/05, page 278 of 884