SH7615 Datasheet, PDF (572/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

12.3 CPU Interface
FRC, OCRA, OCRB, and FICR are 16-bit registers. The data bus width between the CPU and
FRT, however, is only 8 bits. Access of these three types of registers from the CPU therefore
needs to be performed via an 8-bit temporary register called TEMP.
The following describes how these registers are read from and written to:
• Writing to 16-bit Registers
The upper byte is written, which results in the upper byte of data being stored in TEMP. The
lower byte is then written, which results in 16 bits of data being written to the register when
combined with the upper byte value in TEMP.
• Reading from 16-bit Registers
The upper byte of data is read, which results in the upper byte value being transferred to the
CPU. The lower byte value is transferred to TEMP. The lower byte is then read, which results
in the lower byte value in TEMP being sent to the CPU.
When registers of these three types are accessed, two byte accesses should always be performed,
first to the upper byte, then the lower byte. If only the upper byte or lower byte is accessed, the
data will not be transferred properly.
Figure 12.2 and 12.3 show the flow of data when FRC is accessed. Other registers function in the
same way. When reading OCRA and OCRB, however, both upper and lower-byte data is
transferred directly to the CPU without passing through TEMP.
Rev. 2.00, 03/05, page 534 of 884