SH7615 Datasheet, PDF (528/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

CKIO
A24–A0
CS
WE
D31–D0
DACKn
BS
Address output to external
memory space
Write strobe signal to external
memory space
Data output from external
device with DACK
DACK signal (active low) to external
device with DACK
a. External device with DACK to external memory space
CKIO
A24–A0
CS
RD
D31–D0
DACKn
BS
Address output to external
memory space
Read strobe signal to external
memory space
Data output from external
memory space
DACK signal (active low) to external
device with DACK
b. External memory space to external device with DACK
Figure 11.7 DMA Transfer Timing in Single Address Mode
• Dual Address Mode
In dual address mode, both the transfer source and destination are accessed (selectable) by
address. The source and destination can be located externally or internally. The DMAC
accesses the source in the read cycle and the destination in the write cycle, so the transfer is
performed in two separate bus cycles. The transfer data is temporarily stored in the DMAC.
Figure 11.8 shows an example of a transfer between two external memories in which data is
read from one external memory in the read cycle and written to the other external memory in
the following write cycle.
Rev. 2.00, 03/05, page 490 of 884