SH7615 Datasheet, PDF (201/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

5.3.5 Interrupt Priority Level Setting Register E (IPRE)
Interrupt priority level setting register E (IPRE) is a 16-bit read/write register that sets the priority
levels (0 to 15) of on-chip peripheral module interrupts. IPRE is initialized to H'0000 by a reset. It
is not initialized in standby mode.
Bit: 15
14
13
12
11
10
9
8
SCF2IP3 SCF2IP2 SCF2IP1 SCF2IP0 SIO0IP3 SIO0IP2 SIO0IP1 SIO0IP0
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 7
6
5
4
3
2
1
0
SIO1IP3 SIO1IP2 SIO1IP1 SIO1IP0 SIO2IP3 SIO2IP2 SIO2IP1 SIO2IP0
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bits 15 to 12—Serial Communication Interface with FIFO 2 (SCIF2) Interrupt Priority Level 3 to
0 (SCF2IP3 to SCF2IP0): These bits set the serial communication interface with FIFO 2 (SCIF2)
interrupt priority level. There are four bits, so the value can be set between 0 and 15.
Bits 11 to 0—Serial I/O 0 to 2 (SIO0 to SIO2) Interrupt Priority Level 3 to 0 (SIOnIP3 to
SIOnIP0, n = 0 to 2): These bits set the serial I/O 0 to 2 (SIO0 to SIO2) interrupt priority levels.
There are four bits for each interrupt, so the value can be set between 0 and 15.
Table 5.5 shows the relationship between on-chip peripheral module interrupts and interrupt
priority level setting registers.
Table 5.5 Interrupt Request Sources and IPRA to IPRE
Register
Interrupt priority level setting
register A
Interrupt priority level setting
register B
Interrupt priority level setting
register C
Interrupt priority level setting
register D
Interrupt priority level setting
register E
Bits 15 to 12
Reserved
E-DMAC
Bits 11 to 8
DMAC0,
DMAC1
FRT
Bits 7 to 4
WDT, REF
Reserved
IRQ0
IRQ1
IRQ2
TPU0
TPU1
TPU2
SCIF2
SIO0
SIO1
Bits 3 to 0
Reserved
Reserved
IRQ3
SCIF1
SIO2
Rev. 2.00, 03/05, page 163 of 884