SH7615 Datasheet, PDF (427/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

9.2.6 MAC Address Low Register (MALR)
Bit: 31
30
29
...
19
18
17
16
—
—
—
...
—
—
—
—
Initial value: 0
0
0
...
0
0
0
0
R/W: R
R
R
R
R
R
R
Bit:
Initial value:
R/W:
15
MA15
0
R/W
14
MA14
0
R/W
13
MA13
0
R/W
12
MA12
0
R/W
11
MA11
0
R/W
10
MA10
0
R/W
9
MA9
0
R/W
8
MA8
0
R/W
Bit:
Initial value:
R/W:
7
MA7
0
R/W
6
MA6
0
R/W
5
MA5
0
R/W
4
MA4
0
R/W
3
MA3
0
R/W
2
MA2
0
R/W
1
MA1
0
R/W
0
MA0
0
R/W
The lower 16 bits of the 48-bit MAC address are set in MARL. The setting in this register is
normally made in the initialization process after a reset.
Note: The MAC address setting must not be changed while the transmitter and receiver are
enabled. First return the EtherC and E-DMAC modules to their initial state by means of
the SWR bit in the E-DMAC mode register (EDMR), then make the new setting.
Bits 31 to 16—Reserved: These bits are always read as 0. The write value should always be 0.
Bits 15 to 0—MAC Address Bits 15 to 0 (MA15 to MA0): Used to set the lower 16 bits of the
MAC address.
Note: If the MAC address to be set in the SH7615 is 01-23-45-67-89-AB (hexadecimal), the
value set in this register is H'000089AB.
Rev. 2.00, 03/05, page 389 of 884