SH7615 Datasheet, PDF (403/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

8.4.2 Write Access
Write-Through Mode: Writing to external memory is performed regardless of whether or not
there is a cache hit. The write address output to the cache address bus is used for comparison to the
tag address of the cache’s address array. If they match, the write data output to the cache data bus
in the following cycle is written to the cache data array. If they do not match, nothing is written to
the cache data array. The write address is output to the internal address bus 1 cycle later than the
cache address bus. The write data is similarly output to the internal data bus 1 cycle later than the
cache data bus. The CPU waits until the writes on the internal buses are completed (figure 8.5).
Iφ
EX
MA
CPU pipeline
stage
EX
MA
Cache
address bus
Cache
data bus
Internal
address bus
Internal
data bus
Address A Address B
Cache tag comparison
Address A
Data array write
Address A
Address A
EX: Instruction execution
MA: Memory access
Figure 8.5 Write Access (Write-Through)
Address B
Address B
Rev. 2.00, 03/05, page 365 of 884