SH7615 Datasheet, PDF (435/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

9.2.14 CRC Error Frame Counter Register (CEFCR)
Bit: 31
30
29
...
19
18
17
16
—
—
—
...
—
—
—
—
Initial value: 0
0
0
...
0
0
0
0
R/W: R
R
R
...
R
R
R
R
Bit: 15
14
13
12
11
10
9
CEFC15 CEFC14 CEFC13 CEFC12 CEFC11 CEFC10 CEFC9
Initial value: 0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W
8
CEFC8
0
R/W
Bit:
Initial value:
R/W:
7
CEFC7
0
R/W
6
CEFC6
0
R/W
5
CEFC5
0
R/W
4
CEFC4
0
R/W
3
CEFC3
0
R/W
2
CEFC2
0
R/W
1
CEFC1
0
R/W
0
CEFC0
0
R/W
CEFCR is a 16-bit counter that indicates the number of times a frame with a CRC error was
received. When the value in this register reaches H'FFFF (65,535), the count is halted. The counter
value is cleared to 0 by a write to this register (the write value is immaterial).
Bits 31 to 16—Reserved: These bits are always read as 0. The write value should always be 0.
Bits 15 to 0—CRC Error Frame Count 15 to 0 (CEFC15 to CEFC0): These bits indicate the count
of CRC error frames received.
Note: When the Permit Receive CRC Error Frame bit (PRCEF) is set to 1 in the EtherC Mode
Register (ECMR), CEFCR is not incremented by reception of a frame with a CRC error.
Rev. 2.00, 03/05, page 397 of 884