SH7615 Datasheet, PDF (774/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

Table 17.4 Instruction Configuration
Bit 15:
TS3
0
Bit 14:
TS2
0
Bit 13:
TS1
0
1
1
0
1
1
0
0
1
1
0
1
Bit 12:
TS0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Description
EXTEST mode
Reserved
CLAMP mode
HIGHZ mode
SAMPLE/PRELOAD mode
Reserved
Reserved
Reserved
Reserved
Reserved
H-UDI interrupt
Reserved
Reserved
Reserved
IDCODE mode (Initial value)
BYPASS mode
Bits 11 to 0—Reserved: These bits are always read as 0. The write value should always be 0.
Rev. 2.00, 03/05, page 736 of 884