SH7615 Datasheet, PDF (720/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

Bit 2—Input Capture/Output Compare Flag C (TGFC): Status flag that indicates the occurrence of
TGRC input capture or compare match in channel 0.
In channels 1 and 2, bit 2 is reserved. It is always read as 0 and cannot be modified.
Bit 2: TGFC
0
1
Description
[Clearing conditions]
(Initial value)
• When DMAC is activated by TGIC interrupt while DRCR setting in DMAC is
TGI0C
• When 0 is written to TGFC after reading TGFC = 1
[Setting conditions]
• When TCNT = TGRC while TGRC is functioning as output compare
register
• When TCNT value is transferred to TGRC by input capture signal while
TGRC is functioning as input capture register
Bit 1—Input Capture/Output Compare Flag B (TGFB): Status flag that indicates the occurrence of
TGRB input capture or compare match.
Bit 1: TGFB
0
1
Description
[Clearing conditions]
(Initial value)
• When DMAC is activated by TGIB interrupt while DRCR setting in DMAC is
TGI0B
• When 0 is written to TGFB after reading TGFB = 1
[Setting conditions]
• When TCNT = TGRB while TGRB is functioning as output compare
register
• When TCNT value is transferred to TGRB by input capture signal while
TGRB is functioning as input capture register
Rev. 2.00, 03/05, page 682 of 884