SH7615 Datasheet, PDF (695/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

15.4 SIO Interrupt Sources and DMAC
Each SIO channel has four interrupt sources: the receive-overrun-error interrupt (RERI) request,
transmit-underrun-error interrupt (TERI) request, receive-data-full interrupt (RDFI) request, and
transmit-data-empty interrupt (TDEI) request. Table 15.3 shows the interrupt sources and their
relative priorities. The RDFI and TDEI interrupts are enabled by the RIE and TIE bits,
respectively, in SICTR. The RERI and TERI interrupts cannot be disabled.
An RDFI interrupt request is generated when the RDRF bit is set to 1 in SISTR. RDFI can activate
the DMA controller (DMAC) to read the data in SIRDR. RDRF is cleared to 0 automatically when
the DMAC reads data from SIRDR.
A TDEI interrupt request is generated when the TDRE bit is set to 1 in SISTR. TDEI can activate
the DMAC to write the next data to SITDR. TDRE is cleared to 0 automatically when the DMAC
writes data to SITDR.
When TDEI and RDFI interrupt requests are handled by the DMAC, and not by the interrupt
controller, a low priority level should be given to interrupts from the SIO to prevent the interrupt
controller from operating.
When the RERR bit is set to 1 in SISTR, an RERI interrupt request is generated.
When the TERR bit is set to 1 in SISTR, a TERI interrupt request is generated.
Channel interrupt priority levels are set by means of the IRPE register, as described in section 5,
Interrupt Controller (INTC).
Table 15.3 SIO Interrupt Sources
Interrupt Source
RERI
TERI
RDFI
TDEI
Description
Receive overrun error (RERR)
Transmit underrun error (TERR)
Receive data register full (RDRF)
Transmit data register empty (TDRE)
DMAC Activation
Not possible
Not possible
Possible
Possible
Priority
High
Low
Rev. 2.00, 03/05, page 657 of 884