SH7615 Datasheet, PDF (814/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

19.3.1 Register Configuration
Table 19.3 shows the port B register.
Table 19.3 Register Configuration
Name
Port B data register
Abbreviation R/W
PBDR
R/W
Initial Value
H'0000
Address
Access Size
H'FFFFFC8C 8, 16
19.3.2 Port B Data Register (PBDR)
Bit: 15
14
13
12
11
10
9
8
PB15DR PB14DR PB13DR PB12DR PB11DR PB10DR PB9DR PB8DR
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 7
6
5
4
3
2
1
0
PB7DR PB6DR PB5DR PB4DR PB3DR PB2DR PB1DR PB0DR
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
The port B data register (PBDR) is a 16-bit read/write register that stores port B data. Bits
PB15DR to PB0DR correspond to pins PB15 to PB0. When a pin functions as a general output, if
a value is written to PBDR, that value is output directly from the pin, and if PBDR is read, the
register value is returned directly regardless of the pin state. When a pin functions as a general
input, if PBDR is read the pin state, not the register value, is returned directly. If a value is written
to PBDR, although that value is written into PBDR it does not affect the pin state. Table 19.4
shows port B data register read/write operations.
PBDR is initialized to H'0000 by a power-on reset. It is not initialized by a manual reset, in
standby mode or sleep mode.
Rev. 2.00, 03/05, page 776 of 884