SH7615 Datasheet, PDF (480/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

10.2.11 FIFO Depth Register (FDR)
FDR specifies the depth (size) of the transmit and receive FIFOs.
Bit: 31
30
29
...
19
18
17
16
—
—
—
...
—
—
—
—
Initial value: 0
0
0
...
0
0
0
0
R/W: R
R
R
...
R
R
R
R
Bit: 15
14
13
12
11
10
9
8
—
—
—
—
—
—
—
TFD
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R/W
Bit: 7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
RFD
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R/W
Bits 31 to 9—Reserved: These bits are always read as 0. The write value should always be 0.
Bit 8—Transmit FIFO Depth (TFD): Specifies either 256 or 512 bytes as the depth (size) of the
transmit FIFO (which has a maximum capacity of 512 bytes). The setting cannot be changed after
transmission/reception has started.
Bit 8: TFD
0
1
Description
256 bytes
512 bytes
(Initial value)
Bits 7 to 1—Reserved: These bits are always read as 0. The write value should always be 0.
Bit 0—Receive FIFO Depth (RFD): Specifies either 256 or 512 bytes as the depth (size) of the
receive FIFO (which has a maximum capacity of 512 bytes). The actual FIFO depth is 256 times
the set value. The setting cannot be changed after transmission/reception has started.
Bit 0: RFD
0
1
Description
256 bytes
512 bytes
(Initial value)
Rev. 2.00, 03/05, page 442 of 884