SH7615 Datasheet, PDF (551/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

• Cycle-Steal Mode Level Detection
In level detection mode, too, a request cannot be canceled once accepted.
Transfer Width
DREQn Detection
Byte/Word/Longword^* Method
Level Detection
Transfer bus mode
Cycle-steal mode
DACKn output timing Read DACK/write
DACK
Transfer address mode Dual/single mode
Bus cycle
Basic bus cycle
Note: * Do not set a 16-byte unit; operation is not guaranteed if this setting is made.
Clock
Bus cycle
CPU
CPU
DMAC
CPU
DREQn
(Active high)
DACKn
(Active high)
1st
acceptance
Blind zone
Blind zone
2nd
acceptance
Requests acceptable
Figure 11.38 DREQn Pin Input Detection Timing in Cycle-Steal Mode with Level Detection
(Byte/Word/Longword Setting)
Clock
Bus cycle
CPU
CPU
DMAC
H
DMAC
L
DREQn
(Active high)
DACKn
(Active high)
Blind zone
1st
acceptance
Blind zone
2nd
acceptance
DACK
H
DACK
L
Figure 11.39 When a 16-Bit External Device is Connected (Level Detection)
Rev. 2.00, 03/05, page 513 of 884