SH7615 Datasheet, PDF (120/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

Table 2.22 Logic Operation Instructions
Instruction
Instruction Code
AND Rm,Rn
0010nnnnmmmm1001
AND #imm,R0
11001001iiiiiiii
AND.B #imm,@(R0,GBR) 11001101iiiiiiii
NOT
OR
OR
OR.B
Rm,Rn
0110nnnnmmmm0111
Rm,Rn
0010nnnnmmmm1011
#imm,R0
11001011iiiiiiii
#imm,@(R0,GBR) 11001111iiiiiiii
TAS.B @Rn
0100nnnn00011011
TST Rm,Rn
0010nnnnmmmm1000
TST #imm,R0
11001000iiiiiiii
TST.B #imm,@(R0,GBR) 11001100iiiiiiii
XOR Rm,Rn
0010nnnnmmmm1010
XOR #imm,R0
11001010iiiiiiii
XOR.B #imm,@(R0,GBR) 11001110iiiiiiii
Operation
Rn & Rm → Rn
R0 & imm → R0
(R0 + GBR) & imm →
(R0 + GBR)
~Rm → Rn
Rn | Rm → Rn
R0 | imm → R0
(R0 + GBR) | imm →
(R0 + GBR)
If (Rn) is 0, 1 → T,
1 → MSB of (Rn)
Rn & Rm, if the result
is 0, 1 → T
R0 & imm, if the result
is 0, 1 → T
(R0 + GBR) & imm,
if the result is 0, 1 → T
Rn ^ Rm → Rn
R0 ^ imm → R0
(R0 + GBR) ^ imm →
(R0 + GBR)
Cycles T Bit
1
—
1
—
3
—
1
—
1
—
1
—
3
—
4
Test
result
1
Test
result
1
Test
result
3
Test
result
1
—
1
—
3
—
Rev. 2.00, 03/05, page 82 of 884