SH7615 Datasheet, PDF (66/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

Note: * Figures in square brackets indicate the settings of the mode bits (MD0, MD1) in the
PFC in order to select the multiplex functions in port A [0:13] and port B [0:15].
: WDTOVF In a reset, this pin becomes an output pin.
When used for general input/output, attention must be paid to
the polarity of this pin.
1.4 Processing States
State Transitions: The CPU has five processing states: the reset state, exception handling state,
bus-released state, program execution state, and power-down state. Figure 1.4 shows the state
transitions.
From any state when
RES = 0 and NMI = 1
From any state when
RES = 0 and NMI = 0
Power-on reset state
RST = 0, NMI = 0
RST = 0, NMI = 1
Manual reset state
Interrupt or DMA
address error
RST = 1,
NMI = 1
RST = 1,
NMI = 0
Exception-handling state
Reset states
NMI interrupt
Bus request
cleared
Bus
request
Bus-released state
Exception
Bus request
Bus request ^cleared
received
End of
exception
handling
CKPREQ = 1*
Bus request
received
Bus request
cleared
SLEEP
instruction
(SBY = 0)
Program execution state
MSTP
bit
cleared
MSTP
bit set
SBY bit set and
CKPREQ = 0*
SLEEP
instruction
(SBY = 1)
Sleep mode
Standby mode
Module standby
Note: * clock pause function
Power-down state
Figure 1.4 Processing State Transitions
Rev. 2.00, 03/05, page 28 of 884