SH7615 Datasheet, PDF (397/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

Section 8 Cache
8.1 Introduction
This chip incorporates 4 kbytes of four-way, mixed instruction/data type cache memory. This
memory can also be used as 2-kbyte RAM and 2 kbyte mixed instruction/data type cache memory
by making a setting in the cache control register (CCR) (two-way cache mode). CCR can specify
that either instructions or data do not use cache. Both write-through and write-back modes are
supported for cache operation.
Each line of cache memory consists of 16 bytes. Cache memory is always updated in line units.
Four 32-bit accesses are required to update a line. Since the number of entries is 64, the six bits
(A9 to A4) in each address determine the entry. A four-way set associative configuration is used,
so up to four different instructions/data can be stored in the cache even when entry addresses
match. To efficiently use four ways having the same entry address, replacement is provided based
on a pseudo-LRU (least-recently used) replacement algorithm.
The cache configuration is shown in figure 8.1, and addresses in figure 8.2.
Cache address array
Cache data array
Cache
address bus
LRU
information
Tag
address
UV
Cache
data bus
Data (16 bytes/line)
Way 0
Way 1
Way 2
Way 3
64
entries
Tag address
match signal
Internal
address bus
Internal
data bus
V: Valid bit
U: Update bit
Figure 8.1 Cache Configuration
Rev. 2.00, 03/05, page 359 of 884