SH7615 Datasheet, PDF (752/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

Output Compare Output Timing: A compare match signal is generated in the final state in
which TCNT and TGR match (the point at which the count value matched by TCNT is updated).
When a compare match signal is generated, the output value set in TIOR is output at the output
compare output pin (TIOC pin). After a match between TCNT and TGR, the compare match
signal is not generated until the TCNT input clock is generated.
Figure 16.32 shows output compare output timing.
Pφ
TCNT
input clock
TCNT
N
N+1
TGR
N
Compare
match signal
TIOC pin
Figure 16.32 Output Compare Output Timing
Input Capture Signal Timing: Figure 16.33 shows input capture signal timing.
Pφ
Input capture
input
Input capture
signal
TCNT
TGR
N
N+1
N+2
N
N+2
Figure 16.33 Input Capture Input Signal Timing
Rev. 2.00, 03/05, page 714 of 884