SH7615 Datasheet, PDF(44/925 Page) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7600 Series

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SH7615 Datasheet, PDF (44/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7600 Series

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Item

Specifications

Bus state controller â¢ Address space divided into five areas (CS0 to CS4, max. linear 32 Mbytes

(BSC)

each)

ï£§ Memory types such as DRAM, synchronous DRAM, burst ROM, can

be specified for each area

ï£§ Two synchronous DRAM spaces (CS2, CS3); CS3 also supports

DRAM

ï£§ Bus width (8, 16, 32 bits) can be selected for each area

ï£§ Wait state insertion control for each area

ï£§ Control signal output for each area

ï£§ Endian can be set for CS2 and CS4

â¢ Cache

ï£§ Cache area/cache-through area selection by access address

ï£§ Selection of write-through or write-back mode

â¢ Refresh functions

ï£§ CAS-before-RAS refreshing (auto refreshing) or self-refreshing

ï£§ Refresh interval settable by means of refresh counter and clock select

setting

ï£§ Concentrated refreshing according to refresh count setting

(1, 2, 4, 6, 8)

ï£§ Refresh request output possible (REFOUT)

â¢ Direct DRAM interface

ï£§ Multiplexed row address/column address output

ï£§ Fast page mode burst transfer and continuous access when reading

ï£§ EDO mode

ï£§ TP cycle generation to secure RAS precharge time

â¢ Direct synchronous DRAM interface

ï£§ Multiplexed row address/column address output

ï£§ Bank-active mode (valid for CS3 only)

ï£§ Selection of burst read/single write mode or burst read/burst write

mode

â¢ Bus arbitration (BRLS, BGR)

â¢ Refresh counter can be used as interval timer

ï£§ Interrupt request generated on compare match (CMI interrupt request

signal)

Rev. 2.00, 03/05, page 6 of 884

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