SH7615 Datasheet, PDF (171/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

Table 4.6 Bus Cycles and Address Errors
Bus Cycle
Type
Bus
Master Bus Cycle Description
Address Errors
Instruction CPU
fetch
Instruction fetched from even address
Instruction fetched from odd address
None (normal)
Address error
occurs
Instruction fetched from other than on-chip peripheral
module space
None (normal)
Instruction fetched from on-chip peripheral module
space
Address error
occurs
Data
CPU or Word data accessed from even address
read/write DMAC, _{Word data accessed from odd address}
E-DMAC
None (normal)
Address error
occurs
Longword data accessed from a longword boundary None (normal)
Longword data accessed from other than a longword
boundary
Address error
occurs
Access of cache purge space, address array read/write
space, on-chip peripheral module space, or
synchronous DRAM mode setting space by PC-relative
addressing
Address error
occurs
Access of cache purge space, address array read/write
space, data array read/write space, on-chip peripheral
module space, or synchronous DRAM mode setting
space by a TAS.B instruction
Address error
occurs
Byte, word, or longword data accessed in on-chip
None (normal)
peripheral module space at addresses H'FFFFFC00 to
H'FFFFFCFF
Longword data accessed in on-chip peripheral module Address error
space at addresses H'FFFFFE00 to H'FFFFFEFF
occurs
Word or byte data accessed in on-chip peripheral
module space at addresses H'FFFFFE00 to
H'FFFFFEFF
None (normal)
Byte data accessed in on-chip peripheral module space Address error
at addresses H'FFFF0000 to H'FFFFF0FF or
occurs
H'FFFFFF00 to H'FFFFFFFF
Word or longword data accessed in on-chip peripheral
module space at addresses H'FFFF0000 to
H'FFFFF0FF or H'FFFFFF00 to H'FFFFFFFF
None (normal)
Notes: 1. Address errors do not occur during the synchronous DRAM mode register write cycle.
2. 16-byte DMAC transfers use longword accesses.
Rev. 2.00, 03/05, page 133 of 884