SH7615 Datasheet, PDF (447/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

9.3.4 Accessing MII Registers
MII registers in the PHY-LSI are accessed via the SH7615’s PHY interface register (PIR).
Connection is made as a serial interface in accordance with the MII frame format specified in
IEEE802.3u.
MII Management Frame Format: The format of an MII management frame is shown in figure
9.5. To access an MII register, a management frame is implemented by the program in accordance
with the procedures shown in MII Register Access Procedure.
Access Type
Item
PRE
ST
Number of bits
32
2
Read
1..1
01
Write
1..1
01
MII Management Frame
OP PHYAD REGAD TA
2
5
5
2
10 00001 RRRRR Z0
01 00001 RRRRR 10
DATA
16
D..D
D..D
IDLE
X
PRE: 32 consecutive 1s
ST:
Write of 01 indicating start of frame
OP:
Write of code indicating access type
PHYAD: Write of 0001 if the PHY-LSI address is 1 (sequential write starting with the MSB).
This bit changes depending on the PHY-LSI address.
REGAD: Write of 0001 if the register address is 1 (sequential write starting with the MSB).
This bit changes depending on the PHY-LSI register address.
TA:
Time for switching data transmission source on MII interface
(a) Write: 10 written
(b) Read: Bus release (notation: Z0) performed
DATA:
16-bit data. Sequential write or read from MSB
(a) Write: 16-bit data write
(b) Read: 16-bit data read
IDLE:
Wait time until next MII management format input
(a) Write: Independent bus release (notation: X) performed
(b) Read: Bus already released in TA; control unnecessary
Figure 9.5 MII Management Frame Format
MII Register Access Procedure: The program accesses MII registers via the PHY interface
register (PIR). Access is implemented by a combination of 1-bit-unit data write, 1-bit-unit data
read, bus release, and independent bus release. Examples 1 through 4 below show the register
access timing. The timing will differ depending on the PHY-LSI type.
1. The MII register write procedure is shown in figure 9.6 (a).
2. The bus release procedure is shown in figure 9.6 (b).
3. The MII register read procedure is shown in figure 9.6 (c).
Rev. 2.00, 03/05, page 409 of 884