SH7615 Datasheet, PDF (599/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

WDTOVF 13.4.4 System Reset with
WDTOVF RES If a
signal is input to the pin, the device cannot initialize correctly. Avoid logical
WDTOVF RES input of the
output signal to the input pin. To reset the entire system with the
WDTOVF signal, use the circuit shown in figure 13.9.
Reset input
This LSI
RES
Reset signal to
entire system
WDTOVF
WDTOVF Figure 13.9 Example of Circuit for System Reset with
Signal
13.4.5 Internal Reset in Watchdog Timer Mode
If the RSTE bit is cleared to 0 in watchdog timer mode, the chip will not reset internally when a
WTCNT overflow occurs, but WTCNT and WTCSR in the WDT will reset.
13.4.6 Internal Reset by Watchdog Timer (WDT) in Sleep Mode
When the watchdog time counter (WTCNT) overflows in watchdog timer mode, the SH7615
resets (power-on reset or manual reset) the chip internally. However, if WTCNT overflows in
sleep mode, internal reset is not executed properly and exception handling by the reset cannot
start.
Conditions:
• In sleep mode
IT • WDT.WTCSR.WT/ bit = 1 (watchdog timer mode)
• WDT.RSTCSR.RSTE bit = 1 (internal reset enabled)
• WTCNT overflows
Countermeasures: This problem can be avoided by the following countermeasures.
• When sleep mode is not used, use this internal reset function in watchdog timer mode.
RES • When sleep mode is used, reset by an external signal instead of the internal reset function.
WDTOVF RES Note that the
output signal must not be logically input to the pin of this LSI.
Rev. 2.00, 03/05, page 561 of 884