SH7615 Datasheet, PDF (547/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

Acknowledge Signal Output When External Memory Is Set as Burst ROM: When external
memory is set as burst ROM, the acknowledge signal is output synchronous to the DMA address
(no dual writes allowed) (figure 11.32).
Clock
DACKn
(Active high)
Address
bus
DMAC cycle
DMAC cycle
DMAC (1 wait state)
Figure 11.32 DACKn Output in Nibble Accesses of Burst ROM
11.3.7 DREQn Pin Input Detection Timing
In external request mode, DREQn pin signals are usually detected at the falling edge of the clock
pulse (CKIO). When a request is detected, a DMAC bus cycle is produced four cycles later at the
earliest and a DMA transfer performed. After the request is detected, the timing of the next input
detection varies with the bus mode, address mode, DREQn input detection, and the memory
connected.
DREQn Pin Input Detection Timing in Cycle-Steal Mode: In cycle-steal mode, once a request
is detected from the DREQn pin, the request signal is not detected until DACKn signal output in
the next external bus cycle. In cycle-steal mode, request detection is performed from DACKn
signal output until a request is detected.
Once a request has been accepted, it cannot be canceled midway.
The timing from the detection of a request until the next time requests are detectable is shown
below.
• Cycle-Steal Mode Edge Detection
When transfer control is performed using edge detection, perform DREQn/DACKn
handshaking as shown in figure 11.33, and perform DREQn input control so that there is a
one-to-one relationship between DREQn and DACKn. Operation is not guaranteed if DREQn
is input before the corresponding DACKn is output.
If the DACKn signal is output a number of times, the first DACKn signal for the input DREQn
signal indicates the request acceptance start timing, and subsequently each clock edge is
sampled.
Rev. 2.00, 03/05, page 509 of 884