SH7615 Datasheet, PDF (512/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

Bit 1: TE
0
1
Description
DMA has not ended or was aborted
(Initial value)
Cleared by reading 1 from the TE bit and then writing 0
DMA has ended normally (by TCR = 0)
Bit 0—DMA Enable Bit (DE): Enables or disables DMA transfers. In auto-request mode, the
transfer starts when this bit or the DME bit in DMAOR is set to 1. The NMIF and AE bits in
DMAOR and the TE bit must be all set to 0. In external request mode or on-chip peripheral
module request mode, the transfer begins when the DMA transfer request is received from the
relevant device or on-chip peripheral module, provided this bit and the DME bit are set to 1. As
with the auto-request mode, the TE bit and the NMIF and AE bits in DMAOR must all be set to 0.
The transfer can be stopped by clearing this bit to 0. The DE bit is initialized to 0 by a reset and in
standby mode. Its value is retained during a module standby.
Bit 0: DE
0
1
Description
DMA transfer disabled
DMA transfer enabled
(Initial value)
11.2.5 DMA Vector Number Registers 0 and 1 (VCRDMA0, VCRDMA1)
Bit: 31
30
29
…
11
10
9
8
—
—
—
…
—
—
—
—
Initial value: 0
0
0
…
0
0
0
0
R/W: R
R
R
…
R
R
R
R
Bit:
Initial value:
R/W:
7
VC7
—
R/W
6
VC6
—
R/W
5
VC5
—
R/W
4
VC4
—
R/W
3
VC3
—
R/W
2
VC2
—
R/W
1
VC1
—
R/W
0
VC0
—
R/W
DMA vector number registers 0 and 1 (VCRDMA0, VCRDMA1) are 32-bit read/write registers
that set the DMAC transfer-end interrupt vector number. Only the lower eight bits of the 32 are
valid. They are written as 32-bit values, including the upper 24 bits. Values are retained in a reset,
in standby mode, and when the module standby function is used.
Bits 31 to 8—Reserved: These bits are always read as 0. The write value should always be 0.
Rev. 2.00, 03/05, page 474 of 884