SH7615 Datasheet, PDF (526/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

11.3.4 DMA Transfer Types
It can operate in single address mode or dual address mode, as defined by how many bus cycles
the DMAC takes to access the transfer source and transfer destination. The actual transfer
operation timing varies with the DMAC bus mode used: cycle-steal mode or burst mode. The
DMAC supports all the transfers shown in table 11.7.
Table 11.7 Supported DMA Transfers
Destination
Source
External
Device with
DACK
External
Memory
On-Chip
Memory-Mapped Peripheral
External Device Module
On-Chip
Memory
External device
with DACK
External memory
Memory-mapped
external device
On-chip peripheral
module
On-chip memory
Not available
Single
Single
Not available
Not available
Single
Dual
Dual
Dual^*
Dual
Single
Dual
Dual
Dual^*
Dual
Not available Not available
Dual^*
Dual^*
Dual
Dual
Dual^*
Dual^*
Dual^*
Dual
Single: Single address mode
Dual: Dual address mode
Note: * Access size permitted by peripheral module register used as transfer source or transfer
destination (excluding DMAC, BSC, UBC, cache memory, E-DMAC, and EtherC).
Address Modes:
• Single Address Mode
In single address mode, both the transfer source and destination are external; one (selectable) is
accessed by a DACKn signal while the other is accessed by address. In this mode, the DMAC
performs the DMA transfer in one bus cycle by simultaneously outputting a transfer request
acknowledge DACKn signal to one external device to access it, while outputting an address to
the other end of the transfer. Figure 11.6 shows an example of a transfer between external
memory and external device with DACK. That data is written in external memory in the same
bus cycle while the external device outputs data to the data bus.
Rev. 2.00, 03/05, page 488 of 884