SH7615 Datasheet, PDF (237/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

Interrupt clear instruction
Synchronization instruction
•
•
•
LDC instruction
Interrupt disable instruction
Normal instruction
Write completed
Next interrupt can be accepted
DEM
On-chip peripheral
write, min. 1 Icyc
DEM
W
On-chip peripheral
read, min. 1 Icyc
DE
DE
DE
0.5Icyc + 1.0Pcyc
On-chip peripheral interrupt
Figure 5.14 Pipeline Operation when Interrupts are Enabled by Means of SR Modification
In the above figure, the stage in which the instruction fetch occurs cannot be specified
because of the mix of DSP instructions in this chip, so instruction fetch F is omitted in most
cases during pipeline operation.
Rev. 2.00, 03/05, page 199 of 884