SH7615 Datasheet, PDF (272/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

Bit 3—Data Break Enable D (DBED): Selects whether a data bus condition is to be included in the
channel D break conditions.
Bit 3: DBED
0
1
Description
Data bus condition is not included in channel D conditions
Data bus condition is included in channel D conditions
(Initial value)
Bit 2—PC Break Select D (PCBD): Selects whether a channel D instruction fetch cycle break is
effected before or after execution of the instruction.
Bit 2: PCBD
0
1
Description
Channel D instruction fetch cycle break is effected before instruction execution
(Initial value)
Channel D instruction fetch cycle break is effected after instruction execution
Bits 1 and 0—Reserved: These bits are always read as 0. The write value should always be 0.
6.2.20 Branch Flag Registers (BRFR)
Bit: 15
14
13
12
11
10
9
8
SVF
PID2 PID1 PID0
—
—
—
—
Initial value:
0
Undefined Undefined Undefined
0
0
0
0
R/W: R
R
R
R
R
R
R
R
Bit: 7
6
5
4
3
2
1
0
DVF
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
The branch flag registers (BRFR) comprise a set of four 16-bit read-only registers. The BRFR
registers contain flags indicating whether the actual branch addresses (in a branch instruction,
repeat, interrupt, etc.) have been saved in BRSR and BRDR, and a 3-bit pointer indicating the
number of cycles from fetch to execution of the last instruction executed. The BRFR registers
form a FIFO (first-in first-out) queue for PC trace use. The queue is shifted at each branch.
Bits SVF and DVF are initialized by a power-on reset, but bits PID2 to PID0 are not.
Bit 15—Source Verify Flag (SVF): Indicates whether the address and pointer that enable the
branch source address to be calculated have been stored in BRSR. This flag is set when the
instruction at the branch destination address is fetched, and reset when BRSR is read.
Rev. 2.00, 03/05, page 234 of 884