SH7615 Datasheet, PDF (311/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

Bit 9—Bank Active Mode (RASD)
Bit 9: RASD
0
1
Description
For DRAM, RAS is negated after access ends (normal operation)
For synchronous DRAM, a read or write is performed using auto-precharge
mode. The next access always starts with a bank active command
(Initial value)
For DRAM, after access ends RAS down mode is entered in which RAS is left
asserted. When using this mode with an external device connected which
performs writes other than to DRAM, see section 7.6.5, Burst Access
For synchronous DRAM, access ends in the bank active state. This is only
valid for area 3. When area 2 is synchronous DRAM, the mode is always auto-
precharge
Bits 7, 5, and 4—Address Multiplex (AMX2 to AMX0)
• For DRAM interface
Bit 7: AMX2
0
1
Bit 5: AMX1
0
1
0
1
Bit 4: AMX0
0
1
0
1
0
1
0
1
Description
8-bit column address DRAM
9-bit column address DRAM
10-bit column address DRAM
11-bit column address DRAM
Reserved (do not set)
Reserved (do not set)
Reserved (do not set)
Reserved (do not set)
(Initial value)
Rev. 2.00, 03/05, page 273 of 884