SH7615 Datasheet, PDF (221/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

5.3.26 Vector Number Setting Register T (VCRT)
Vector number setting register T (VCRT) is a 16-bit read/write register that sets the serial I/O 2
(SIO2) receive overrun error interrupt and transmit underrun error interrupt vector numbers (0 to
127).
VCRT is initialized to H'0000 by a reset. It is not initialized in standby mode.
Bit:
Initial value:
R/W:
15
14
13
12
11
10
9
8
— RER2V6 RER2V5 RER2V4 RER2V3 RER2V2 RER2V1 RER2V0
0
0
0
0
0
0
0
0
R
R/W R/W R/W R/W R/W R/W R/W
Bit: 7
6
5
4
3
2
1
0
— TER2V6 TER2V5 TER2V4 TER2V3 TER2V2 TER2V1 TER2V0
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R/W R/W R/W R/W R/W R/W R/W
Bits 15 and 7—Reserved: These bits are always read as 0. The write value should always be 0.
Bits 14 to 8—Serial I/O 2 (SIO2) Receive Overrun Error Interrupt Vector Number 6 to 0
(RER2V6 to RER2V0): These bits set the vector number for the serial I/O 2 (SIO2) receive
overrun error interrupt. There are seven bits, so the value can be set between 0 and 127.
Bits 6 to 0—Serial I/O 2 (SIO2) Transmit Underrun Error Interrupt Vector Number 6 to 0
(TER2V6 to TER2V0): These bits set the vector number for the serial I/O 2 (SIO2) transmit
underrun error interrupt. There are seven bits, so the value can be set between 0 and 127.
Rev. 2.00, 03/05, page 183 of 884