SH7615 Datasheet, PDF (254/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

6.2.9 Break Data Register C (BDRC)
BDRCH
Bit:
Initial value:
R/W:
15
BDC31
0
R/W
14
BDC30
0
R/W
13
BDC29
0
R/W
12
BDC28
0
R/W
11
BDC27
0
R/W
10
BDC26
0
R/W
9
BDC25
0
R/W
8
BDC24
0
R/W
Bit:
Initial value:
R/W:
7
BDC23
0
R/W
6
BDC22
0
R/W
5
BDC21
0
R/W
4
BDC20
0
R/W
3
BDC19
0
R/W
2
BDC18
0
R/W
1
BDC17
0
R/W
0
BDC16
0
R/W
BDRCL
Bit:
Initial value:
R/W:
15
BDC15
0
R/W
14
BDC14
0
R/W
13
BDC13
0
R/W
12
BDC12
0
R/W
11
BDC11
0
R/W
10
BDC10
0
R/W
9
BDC9
0
R/W
8
BDC8
0
R/W
Bit:
Initial value:
R/W:
7
BDC7
0
R/W
6
BDC6
0
R/W
5
BDC5
0
R/W
4
BDC4
0
R/W
3
BDC3
0
R/W
2
BDC2
0
R/W
1
BDC1
0
R/W
0
BDC0
0
R/W
Break data register C (BDRC) consists of two 16-bit readable/writable registers: break data
register CH (BDRCH) and break data register CL (BDRCL). BDRCH specifies the upper half
(bits 31 to 16) of the data used as a channel C break condition, and BDRCL specifies the lower
half (bits 15 to 0). The data bus connected to the X/Y memory can also be specified as a break
condition by making a setting in the XYEC bit/XYSC bit in break bus cycle register C (BBRC).
When XYEC = 1, the upper 16 bits (BDC31 to BDC16) of BDRC specify the X data bus, and the
lower 16 bits (BDC15 to BDC0) specify the Y data bus.
Rev. 2.00, 03/05, page 216 of 884