SH7615 Datasheet, PDF (197/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

5.3 Register Descriptions
5.3.1 Interrupt Priority Level Setting Register A (IPRA)
Interrupt priority level setting register A (IPRA) is a 16-bit read/write register that assigns priority
levels from 0 to 15 to on-chip peripheral module interrupts. IPRA is initialized to H'0000 by a
reset. It is not initialized in standby mode. Unless otherwise specified, ‘reset’ refers to both power-
on and manual resets throughout this manual.
Bit: 15
14
13
12
11
10
9
8
—
—
—
— DMAC DMAC DMAC DMAC
IP3
IP2
IP1
IP0
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R/W R/W R/W R/W
Bit: 7
6
5
4
3
2
1
0
WDT WDT WDT WDT
—
—
—
—
IP3
IP2
IP1
IP0
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W
R
R
R
R
Bits 15 to 12—Reserved: These bits are always read as 0. The write value should always be 0.
Bits 11 to 8—Direct Memory Access Controller (DMAC) Interrupt Priority Level 3 to 0
(DMACIP3 to DMACIP0): These bits set the direct memory access controller (DMAC) interrupt
priority level. There are four bits, so levels 0 to 15 can be set. The same level is set for both two
DMAC channels. When interrupts occur simultaneously, channel 0 has priority.
Bits 7 to 4—Watchdog Timer (WDT) Interrupt Priority Level 3 to 0 (WDTIP3 to WDTIP0):
These bits set the watchdog timer (WDT) interrupt priority level and bus state controller (BSC)
interrupt priority level. There are four bits, so levels 0 to 15 can be set. When WDT and BSC
interrupts occur simultaneously, the WDT interrupt has priority.
Bits 3 to 0—Reserved: These bits are always read as 0. The write value should always be 0.
Rev. 2.00, 03/05, page 159 of 884