SH7615 Datasheet, PDF (325/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

7.4.2 Wait State Control
The number of wait states inserted into ordinary space access states can be controlled using the
WCR1, WCR2, BCR1 and BCR3 register settings. When the Wn1 and Wn0 wait specification bits
in WCR1, WCR2 for the given CS space are 01 or 10, software waits are inserted according to the
wait specification. When Wn1 and Wn0 are 11, wait cycles are inserted according to the long wait
specification bit AnLW in BCR1, BCR3. The long wait specification in BCR1, BCR3 can be
made independently for CS0, CS1 and CS4 spaces, but the same value must be specified for CS2
and CS3 spaces. All WCR1 specifications are independent. By means of WCR1, WCR2, BCR1,
and BCR3, a Tw cycle is inserted as a wait cycle as long as the number of specified cycles at the
wait timing for ordinary access space shown in figure 7.13. The names of the control bits that
specify Tw for each CS space are shown in table 7.5.
CKIO
T₁
Tw
T₂
A24–A0
CSn
RD/WR
Read
RD
D31–D0
Write
WEn
D31–D0
BS
DACKn*
Note: * DACKn waveform when active–low is specified.
Figure 7.13 Wait Timing of Ordinary Space Access (Software Wait Only)
Rev. 2.00, 03/05, page 287 of 884