SH7615 Datasheet, PDF (142/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

2.6 Usage Notes
1. When DSP instructions are not used, execute the dummy instruction as follows to decrease
operation current.
This dummy instruction is executed in initial program.
PCLR
A0 ; Clear the A0 register.
PSHA #5, A0 ; 5 bit shift to left.
2. When the S bit of SR is changed after the DSP instructions are executed, pipeline is not
executed exactly.
Execute the processing as described in either A or B below.
A. After the DSP instructions are executed, don’t change the S bit of SR register.
B. Insert the NOP instruction before the LDC Rn, SR instruction.
Example:
PSHA #1,A0
PINC X0,A0 MOVX.W A1,@R5
NOP
LDC R0,SR
3. When a double-length multiply instruction (MUL.L, DMULU.L, or DMULS.L) or a double-
length multiply-and-accumulate instruction (MAC.L) is executed in combination with a DSP
operation instruction, a malfunction may occur. See the following conditions and
countermeasures.
Conditions:
When the following A and B conditions are both satisfied, the instruction shown in item b in B
below may be executed incorrectly.
A. An instruction in the on-chip memory or the cache is executed.
B. The following instructions are executed in the order of a, b, and c.
a. Double-length multiply instruction (MUL.L, DMULU.L, or DMULS.L) or double-
length multiply-and-accumulate instruction (MAC.L)
b. DSP operation instruction other than PMULS, PSTS, and PLDS
Note: The following instructions are DSP operation instructions other than PMULS,
PSTS, and PLDS:
PABS, PADD, PADDC, PAND, PCLR, PCMP, PCOPY, PDEC, PDMSB,
PINC, PNEG, POR, PRND, PSHA, PSHL, PSUB, PSUBC, and PXOR
c. PMULS, PSTS, or PLDS
Rev. 2.00, 03/05, page 104 of 884