SH7615 Datasheet, PDF (466/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

Bit 24—Receive Frame Counter Overflow (RFCOF): Indicates that the receive FIFO frame
counter has overflowed.
Bit 24: RFCOF Description
0
Receive frame counter has not overflowed
(Initial value)
1
Receive frame counter overflow (interrupt source)
Note:
The receive FIFO in the E-DMAC can hold up to eight frames. If a ninth frame is received
when there are already eight frames in the receive FIFO, the receive frame counter
overflows and the ninth frame is discarded. Discarded frames are counted by the missed-
frame counter register. The eight frames in the receive FIFO are retained, and are
transferred to memory when DMA transfer becomes possible. When the frame counter
value falls below 8, another frame is received.
Bit 23—Reserved: These bits are always read as 0. The write value should always be 0.
Bit 22—EtherC States Register Interrupt (ECI): Indicates that an interrupt due to an EtherC status
register (ECSR) source has been detected.
Bit 22: ECI
Description
0
EtherC status interrupt source not detected
(Initial value)
1
EtherC status interrupt source detected (interrupt source)
Note: EESR is a read-only register. When this register is cleared by a source in ECSR in the
EtherC, this bit is also cleared.
Bit 21—Frame Transmit Complete (TC): Indicates that all the data specified by the transmit
descriptor has been transmitted to the EtherC. The transfer status is written back to the relevant
descriptor. When 1-frame transmission is completed for 1-frame/1-buffer processing, or when the
last data in the frame is transmitted and the transmission descriptor valid bit (TACT) in the next
descriptor is not set for multiple-frame buffer processing, transmission is completed and this bit is
set to 1. After frame transmission, the E-DMAC writes the transmission status back to the
descriptor.
Bit 21: TC
Description
0
Transfer not complete, or no transfer directive
(Initial value)
1
Transfer complete (interrupt source)
Note: As data is sent onto the line by the PHY-LSI from the EtherC via the MII, the actual
transmission completion time is longer.
Rev. 2.00, 03/05, page 428 of 884