SH7615 Datasheet, PDF (566/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

12.2 Register Descriptions
12.2.1 Free-Running Counter (FRC)
Bit: 15
14
13
…
3
2
1
0
…
Initial value: 0
0
0
…
0
0
0
0
R/W: R/W R/W R/W
…
R/W R/W R/W R/W
FRC is a 16-bit read/write register. It increments upon input of a clock. The input clock can be
selected using clock select bits 1 and 0 (CKS1, CKS0) in TCR. FRC can be cleared upon compare
match A.
When FRC overflows (H'FFFF → H'0000), the overflow flag (OVF) in FTCSR is set to 1. FRC
can be read or written to by the CPU, but because it is 16 bits long, data transfers involving the
CPU are performed via a temporary register (TEMP). See section 12.3, CPU Interface, for more
detailed information.
FRC is initialized to H'0000 by a reset, in standby mode, and when the module standby function is
used.
12.2.2 Output Compare Registers A and B (OCRA and OCRB)
Bit: 15
14
13
…
3
2
1
0
…
Initial value: 1
1
1
…
1
1
1
1
R/W: R/W R/W R/W
…
R/W R/W R/W R/W
OCR is composed of two 16-bit read/write registers (OCRA and OCRB). The contents of OCR are
always compared to the FRC value. When the two values are the same, the output compare flags
in FTCSR (OCFA and OCFB) are set to 1.
When the OCR and FRC values are the same (compare match), the output level values set in the
output level bits (OLVLA and OLVLB) are output to the output compare pins (FTOA and FTOB).
After a reset, FTOA and FTOB output 0 until the first compare match occurs.
Because OCR is a 16-bit register, data transfers involving the CPU are performed via a temporary
register (TEMP). See section 12.3, CPU Interface, for more detailed information.
OCR is initialized to H'FFFF by a reset, in standby mode, and when the module standby function
is used.
Rev. 2.00, 03/05, page 528 of 884